Overlay Contact

The whole model lives on the chip.

A chip built around the models it runs. The whole model sits on the chip, so it never fetches weights from off-chip memory.

~13,000–15,000 tokens a second for one user, at 4 bitsest.tokens/s, one userBefore silicon. 4-bit quality still trails GPU 4-bit on code; at 8 bits, ~7,000–8,000est. B200 on a standard engine: ~890 at FP8measured. A tuned GPU can match or beat our 8-bit design on structured outputest.
Watch the raceTalk to us
IN · embedOUT · head + sampler
Concept of where we're heading, not silicon. Numbers are for our first chip (all-SRAM). Die count schematic. Drag to rotate.

Serving one user, a GPU waits on memory.

It fetches the weights from memory every step. Ours stay on the chip.

A GPU, serving one user

weights · every stepHBMGPUtokens
B200 · one user · standard engine~890 tok/ssame modelmeasured

The Overlay chip

weights on the chip: SRAM todayROM + SRAM directionOVERLAY CHIPtokens
Overlay · one user · pre-silicon~13,000–15,000 tok/ssame model, 4-bitest. · below GPU 4-bit quality on code

Rewritable today. Etched where it's stable, later.

Today we build the chip and its compiler around released models. Next, we co-design the model with the chip. Our first chip is all-SRAM. Etching a model's base weights is a direction we're testing.

  1. Model

    The model as released. Co-designed next.

  2. Compiler

    Places each part of the model.

  3. SRAM WEIGHTSevery weight rewritablePER-USERupdatesfine-tunes

    Our SRAM die

    Every weight in rewritable SRAM.

  4. Verified

    Bit-exact in simulation.

  5. Silicon

    Test chip next.

One user, two machines.

An agent reasons through a step. Watch who finishes.

B200 · one user · standard engine~890 tok/smeasured
B200 · one user · tuned engine~2,600–4,400 tok/sest.
Overlay · one user · 4-bit · pre-silicon~13,000–15,000 tok/sest.
Illustrative, slowed 150×. Our speed is an estimate before silicon; at 4 bits our quality still trails GPU 4-bit on code.

Simulated today. Silicon next.

The design runs bit-exact in simulation today. Test silicon is next. A white paper will follow when the time is right.

  1. NowSoftware and simulation
  2. NextTest silicon
  3. ThenThe product die

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